Semiconductor memory devices such as dynamic random access memory (DRAM) devices may be programmable and erasable, such that binary data may be repeatedly stored in and/or read from the semiconductor devices. A typical cell of a semiconductor memory device may include one transistor and one capacitor. The capacitor may have a storage electrode, a dielectric layer and a plate electrode. To increase the ability of a semiconductor memory device to store electric charge (which is representative of data stored by the device), the capacitance of the capacitor may be increased.
Recently, the degree of integration of DRAM devices has reached the gigabyte scale, which may require a corresponding decrease in the cell area of DRAM devices. In order to increase the density of DRAM devices formed on a single substrate, various alternative capacitor geometries have been investigated. For example, to save space on a semiconductor substrate, capacitors have been designed in which the opposing plates of the capacitor extend in a direction perpendicular to the semiconductor substrate instead of parallel to the substrate. Accordingly, capacitors having various structures such as a tube-shaped structure, a cylindrical structure and/or a mesh-shaped structure have been proposed in an attempt to form capacitors having a desired capacitance and area. When DRAM devices have a critical dimension of below about 0.11 μm, the cell area of the DRAM device is also drastically reduced, which means that in order to have a desired capacitance, the capacitor may have a very large aspect ratio (i.e. a very large ratio of height to width). When capacitors in a DRAM device have a considerably large aspect ratio, adjacent capacitors may become tilted toward each other or even fall down, which may cause an electrical short between adjacent capacitors. Such a condition is known as a 2-bit failure of capacitors.
FIG. 1 is a cross-sectional view illustrating storage electrodes 14 of conventional cylindrical capacitors. Referring to FIG. 1, a conventional cylindrical capacitor 1 includes a storage electrode 14 contacting a contact pad 12 formed on a semiconductor substrate 10. The storage electrode 14 of the capacitor may be electrically connected through the contact pad 12 to a metal oxide semiconductor (MOS) transistor (not shown) formed on the semiconductor substrate 10.
To increase the capacitance of the capacitor, the height of the storage electrode 14 may be increased. However, when the height of the storage electrode 14 becomes large, the storage electrode 14 may lean on an adjacent storage electrode 14, or adjacent storage electrodes 14 may fall down toward each other as shown by the dotted lines in FIG. 1. This 2-bit failure between adjacent storage electrodes 14 may cause an electrical failure of the semiconductor device.
In order to reduce the likelihood of a failure such as a 2-bit failure described above, a stabilizing member having a mesh structure may be formed to enclose the storage electrode of a capacitor. Adjacent stabilizing members may be connected to each other in an attempt to prevent the storage electrodes from falling down or leaning on each other.
In forming the stabilizing member, a first mold layer, a second mold layer and a third mold layer may be sequentially formed on a semiconductor substrate. The mold layers may be selectively etched to form holes therethrough which expose a contact region of the semiconductor substrate. After a conductive layer and a sacrificial layer are formed to fill the holes, the conductive layer and the sacrificial layer may be partially removed by a chemical mechanical polishing (CMP) process until the third mold layer is exposed, thereby forming storage electrodes in the holes. When the third mold layer is removed, the second mold layer and upper portions of the storage electrodes may be exposed. A silicon oxide layer may be formed on the second mold layer and the exposed portions of the storage electrodes. Then, the silicon oxide layer may be anisotropically etched to form spacers on sidewalls of the storage electrodes. Using the spacers as etching masks, the second mold layer may be partially etched to thereby form stabilizing members enclosing the upper portions of the storage electrodes.
However, the silicon oxide layer used to form the spacers may have poor step coverage. In addition, the surface profile of the mold layers may cause a loading effect on the silicon oxide layer. As a result, the stabilizing members may not be uniformly formed on the sidewalls of the storage electrodes. Additionally, the CMP process used for forming the storage electrodes may cause a dishing effect to occur, which may cause the storage electrodes to have non-uniform heights. The foregoing problems may cause the spacers to be non-uniform. Thus, forming uniform stabilizing members may be difficult.